
R2J20702NP Target Specification
REJ03G1782-0401 Rev.4.01 Page 5 of 27
Jun 17, 2010
Pin Description
Pin Name Pin No. Description Remarks
VIN 10 to 20 Input voltage for the buck converter.
SW 9, 21, 40 to 48
Switching node. Connect a choke coil between the
SW pin and dc output node of the converter.
PGND 22 to 39 Ground of the power stage.
Should be externally connected to
SGND.
SGND 6, 52 Ground of the IC chip.
Should be externally connected to
PGND.
VCIN 7 Input voltage for the control circuit. Should be externally connected to VIN.
BOOT 8
Bootstrap voltage pin. A bootstrap capacitor should
be connected between the BOOT and SW pin.
To be supplied +5 V through the
internal SBD.
REG5 5 +5 V logic power-supply output.
Requires decoupling from the GND
plane by a capacitance 0.1 F.
ON/OFF 50 Signal disable pin.
Disabled when ON/OFF pin is in the
low state.
IREF 4 Reference current generator for the IC.
Should be connected via 27 k to the
SGND pin.
CT 55
Timing capacitor pin for the oscillator. This pin has a
select function for operation in slave mode.
If the pin voltage is <1 V or >4 V, the IC
operates in slave mode.
SYNC 49 I/O pin for synchronous operation.
TRK-SS 56 Start-up timing control input.
FB 1 Feedback voltage input for the closed loop.
When IC works as a slave module in
multiphase power supply, FB pin
should connected to REG5 pin.
EO 3 Error amplifier output pin.
Requires connection to an RC circuit
for loop compensation.
Ishare 2 For current-sharing bus.
Simply connect the Ishare pins of all
devices to get balanced current.
RAMP 54
RAMP signal input pin for peak current mode PWM
control.
CS 53 Current output pin of active current sensing circuit.
Appropriate resistance is required
between CS and the GND plane.
DRV5 51
+5.25 V generator output for driving power MOS
FETs.
Requires decoupling from the GND
plane by a capacitance from 0.1 F to
1.0 F.
Comentarios a estos manuales